Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-11-07

2000-11-07

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257758, H01L 31119

Patent

active

061440558

ABSTRACT:
A dynamic memory device includes a buried plate-wiring connected to a plate electrode of a memory cell. A plate potential is supplied to the buried plate-wiring via a plate potential supply-wiring. A connection node of the buried plate-wiring and the plate potential supply-wiring is arranged at a side of the memory cell array opposed to a side of a row decoder array.

REFERENCES:
patent: 4918502 (1990-04-01), Kaga et al.
patent: 5151772 (1992-09-01), Takahashi et al.
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5452244 (1995-09-01), Mohan Rao
patent: 5502320 (1996-03-01), Yamada
patent: 5544101 (1996-08-01), Houston
patent: 5600591 (1997-02-01), Takagi
patent: 5691550 (1997-11-01), Kohyama
patent: 5867446 (1999-02-01), Konishi et al.
patent: 5874332 (1999-02-01), Ema
IEEE Transactions on Electron Device vol. 35, No. 8, Aug. 1988, pp. 1257-1263, "Half-Vcc Sheath Plate Capacitor DRAM Cell With Self-Aligned Buried Plate-Wiring," T. Kaga et al.
International Electron Devices Meeting 1993, A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned Buried Strap (BEST), L. Nesbit et al.
Weste et al. "Principles of CMOS VLSI Design," plate 13, 1995.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1643792