CMOS integrated circuit protected from latch-up phenomenon

Details CMOS integrated circuit protected from latch-up phenomenon CMOS integrated circuit protected from latch-up phenomenon

1985-09-11

1988-02-02

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307291, 307363, 307443, 307451, 361 91, H03K 326, H03K 329, H03K 5153, H02H 320

Patent

active

047230819

ABSTRACT:
A CMOS integrated circuit formed in a first semiconductor substrate is supplied with a power through a power control circuit formed in a second semiconductor substrate. The power control circuit is, for example, a flip-flop using the CMOS integrated circuit as one load and detects that a resistance value of the one load is decreased below a predetermined value and decreases power supplied to the CMOS integrated circuit in response to the detection.

REFERENCES:
patent: 4353105 (1982-10-01), Black

Affiliated with

Also associated with

Rating

CMOS integrated circuit protected from latch-up phenomenon does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS integrated circuit protected from latch-up phenomenon, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS integrated circuit protected from latch-up phenomenon will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1637115