Non-volatile memory circuits and architecture

Details Non-volatile memory circuits and architecture Non-volatile memory circuits and architecture

1991-06-12

1994-01-11

Hille, Rolf

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 36518901, 36518903, 36523004, G11C 1134, G11C 800

Patent

active

052787850

ABSTRACT:
The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. It includes a decoding scheme wherein the memory chip has a row address bit which is used for the row decoding also participating in the bit line decoding process. The invention comprises only one row decoder providing the required voltages to the read word lines during reading, programming and page and flash erase operations. The invention expands the feature of the reduction in programming time of non-volatile memories from a single cell to the entire row of cells that program using hot electrons. The invention reduces the diffusion isolation spacing between bit-lines by using shield transistors. A current mirror with multiple branches is used as part of a power switch to control the supply of 5 or 12 volts to various circuit block of the EEPROM chip. According to another aspect of the invention the asymmetry in programming of split gate EEPROM is used to reverse bias the cell so that a plurality of digital bits that were programmed in the cell by an integrated D/A converter according to a curve, are read out by an A/D converter with large voltage difference between logical states.

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