Semiconductor memory device having voltage stress testing capabi

Details Semiconductor memory device having voltage stress testing capabi Semiconductor memory device having voltage stress testing capabi

1992-03-10

1994-05-31

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

365201, 3072961, 3072963, G11C 700

Patent

active

053175328

ABSTRACT:
A semiconductor memory device which comprises memory cells arranged in rows and columns on a semiconductor substrate, each having one transistor and one capacitor, word lines each connected to memory cells in the same row, bit lines each connected to memory cells in the same column, a plate voltage generating circuit for generating a capacitor plate voltage at the time of normal operation, a negative pulse generating circuit responsive to a control signal supplied thereto at the time of voltage stress testing, for generating a pulse voltage of negative polarity, switch circuits for supplying the pulse voltage of negative polarity output from the negative pulse generating circuit, to the plate electrodes of the capacitors of all memory cells simultaneously, in place of the output of the plate voltage generating circuit, and a switch control circuit responsive to a control signal supplied thereto during voltage stress testing, for controlling the switch circuits.

REFERENCES:
patent: 4751679 (1988-06-01), Dehganpour
patent: 4839865 (1989-06-01), Sato et al.
patent: 5051995 (1991-09-01), Tobita
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct., 1987 pp. 643-650, "A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell".

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