Low voltage, low power operable static random access memory devi

Details Low voltage, low power operable static random access memory devi Low voltage, low power operable static random access memory devi

1997-03-27

1998-09-22

Le, Vu A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365190, G11C 700

Patent

active

058124454

ABSTRACT:
A memory cell is formed by flip-flop connection of a load transistor pair of a first load transistor and a second load transistor and a drive transistor pair of a first drive transistor and a second drive transistor. A first switch which is controlled by a wordline and a second switch which is activated only at the time of the write operation are connected in series to a first memory node. The second switch is serially coupled between the first memory node and the first drive transistor. An electric current is injected from a sense amplifier into a bitline pair selected at the time of the read operation, to detect an impedance which varies with the signal potential at the first memory node.

REFERENCES:
patent: 4779226 (1988-10-01), Haraszti
patent: 4779231 (1988-10-01), Holzapfel et al.

Affiliated with

Also associated with

Rating

Low voltage, low power operable static random access memory devi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low voltage, low power operable static random access memory devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low voltage, low power operable static random access memory devi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1629619