Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-03-15
1998-09-22
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257413, 257409, H01L 2976
Patent
active
058118640
ABSTRACT:
A planarized integrated circuit and method for making it are disclosed. The method includes forming portions of a transistor structure that extend to an elevation on an integrated circuit substrate above intermediate regions above the substrate. The portions have an oxide layer on their top surfaces. A layer of polysilicon is formed overall, including in the intermediate regions, to a depth in the intermediate regions larger than the elevation to which the portions of the transistor structure extend. A chemical-mechanical-polishing step is performed on the polysilicon overall to a depth at least extending to the oxide layer on the transistor portions to create a first planarized surface. In subsequent processing, a layer of oxide may be formed over the planarized surface, with source/drain extension regions patterned in the layer of oxide and underlying structures to the surface of the substrate. Source and drain region impurities are implanted for an MOS transistor in the source/drain extension regions, and a second layer of spacer oxide is formed overall. Portions of the spacer oxide are removed in bottom portions of the source/drain extension regions, and a layer of polysilicon is formed overall to a depth deeper than a depth of the source/drain extension regions. A chemical-mechanical-polishing step is performed on the polysilicon overall to a depth at least extending to the second layer of spacer oxide to create a second planarized surface.
REFERENCES:
patent: 5606202 (1997-02-01), Bronner et al.
Fury, Michael, A., Emerging developments in CMP for semiconductor planarization, Apr. 1995.
Shibahara, et al., Trench Isolation with .gradient. (NABLA)--Shaped Buried Oxide for 256MEGA--Bit Drams, 1992 IEEE.
Fazan, et al., A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs, 1993 IEEE.
Kikuta, et al., Multilevel Planaraized-Trench-Aluminum (PTA) Interconnection Using Reflow Sputtering and Chemical Mechanical Polishing, 1993 IEEE.
Potter Roy
Thomas Tom
United Memories Inc.
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