Read circuit having a limited-bandwidth amplifier for holding th

Details Read circuit having a limited-bandwidth amplifier for holding th Read circuit having a limited-bandwidth amplifier for holding th

1988-10-05

1990-02-20

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

365149, 36518905, 365191, 36518906, 307243, 307601, G11C 700

Patent

active

049032410

ABSTRACT:
An amplifier (63) at the output (41) of a delay circuit (3) comprising capacitive memory elements (5, 7, 9, 11) which can be successively written and successively read in a manner which is delayed with respect to the writing sequence is formed as a differential amplifier having a special negative feedback (73, 75) and a double sampling circuit (55, 57) at its two inputs (61, 65) to obtain a sufficiently high output voltage and to serve as a hold circuit so that no stringent requirement need to be imposed on the bandwidth of the amplifier.

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patent: 4651027 (1987-03-01), Herzl
patent: 4679168 (1987-07-01), Conway et al.
patent: 4710654 (1987-12-01), Saitoh et al.
patent: 4712203 (1987-12-01), Saito et al.
patent: 4716548 (1987-12-01), Mochizuki
patent: 4760346 (1988-07-01), Kultgen et al.
patent: 4775914 (1988-10-01), Incardona
patent: 4797576 (1989-01-01), Asazawa
patent: 4814640 (1989-03-01), Miyake
Transport Delay Simulation, by K. Soe Hojberg, Instruments & Control Systems, Jun. 1966, p. 165.
Variable Electronic Allpass Delay Networks by R. K. P. Galpin, Electronics Letters, 4, NR 7, Apr. 5, 1968, pp. 137-139.
Technology Update, 8029 Electronic Engineering 50 (1985) Jul., No. 703, London, Great Britain, p. 25.
Fernseh-Und Kino-Technick, 30, Jahrgang, No. 3, pp. 81-85, by G. Brand.

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