Electronic digital logic circuitry – Threshold
Patent
1997-09-02
1998-10-27
Santamauro, Jon
Electronic digital logic circuitry
Threshold
326 59, H03K 1923, H03K 1900
Patent
active
058282289
ABSTRACT:
A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The output produces output NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The threshold switching circuit triggers changes of the output signal state to NULL in response to the states of all the input signals becoming NULL. The threshold switching circuit triggers changes of the output signal state to the meaningful state when the number of the input signals in the meaningful state exceeds a threshold number. The threshold switching circuit triggers changes of the output signal state to the third state when (i) fewer than all input signals are in the NULL state, and (ii) fewer than the threshold number of input signals are in the meaningful state.
REFERENCES:
patent: 3715603 (1973-02-01), Lerch
patent: 4542525 (1985-09-01), Hopf
patent: 4845653 (1989-07-01), Furtek
patent: 5121003 (1992-06-01), Williams
patent: 5305463 (1994-04-01), Fant et al.
patent: 5382844 (1995-01-01), Knauer
patent: 5386424 (1995-01-01), Driscoll et al.
patent: 5664212 (1997-09-01), Fant et al.
Wojcik et al., On the Design of Three Valued Asynchronous Module, IEEE Transactions on Computers, vol. C-29, No. 10, Oct. 1980, pp. 889-898.
Stephen H. Unger, Asynchronous Sequential Switching Circuits, 1969, pp. 221,229.
Carver Mead, Lynn Conway, Introduction to VLSI Systems, 1980, pp. 242-262.
Ivan E. Sutherland, Micropipelines, June 1989, vol. 32, No. 6, Communications of the ACM.
Tadashi Shibata & Tadahiro Ohmi, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions On Electron Devices, Dec. 1992, vol. 39, No. 6, pp. 1444-1455.
Mark Edward Dean, Strip: A Self-Timed Risc Processor, Jun. 1992.
Daniel Hampel & Robert Winder, Threshold Logic, IEEE Spectrum, May 1971, pp. 32-39.
Janusz A. Brzozowski & Carl-Johan H. Seger, Asynchronous Circuits--Monographs in Computer Science, Springer-Verlag New York, Inc., 1995, New York, NY.
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp. 309-322.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transations on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, Integration, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassen, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Burford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Wiliams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
David E. Muller, Asynchronous Logics and Application to Information Processing, Stanford University Press, Switching Theory In Space Technology, pp. 289-297, 1963.
Marinder Pal Singh, A Design Methodology For Self-Timed Systems, Massachusetts Institute of Technology, MIT/LCS/TR-258, Feb. 1981.
T.S. Anatharaman, A Delay Insensitive Regular Expression Recognizer, Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-89-109, Jan. 1989.
Jens Sparso, et al., Design of Delay Insensitive Circuits Using Multi-Ring Stuctures, European Design Automation Conference, IEEE 0-8186-2780, pp. 15-20, Aug. 1992.
Lawrence G. Heller, et al., Cascode Voltage Switch Logic: A Different CMOS Logic Family, ISSCC 84 Digest of Technical Papers, IEEE, pp. 16-17, Feb. 1984.
Lars S. Nielsen and Jens Sparso, A Low-Power Asynchronous Data-Path For A FIR Filter Bank, IEEE 0-8186-7298-6/96, pp. 197-207, Jun. 1996.
Brandt Scott A.
Fant Karl M.
Santamauro Jon
Theseus Logic Inc.
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