Method of making an integrated circuit which uses an etch stop f

Details Method of making an integrated circuit which uses an etch stop f Method of making an integrated circuit which uses an etch stop f

1997-10-23

1998-10-27

Tsai, Jey

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438634, 438637, 438700, 438734, 438738, 438740, H01L 214763

Patent

active

058277765

ABSTRACT:
A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

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IBM Technical Disclosure Bulletin entitled, "Damascene: Optimized Etch Stop Structure and Method," vol. 36, No. 11, p. 649.
IBM Technical Disclosure Bulletin entitled, "Displaced Metal Conductor," vol. 36, No. 11, pp. 599-602.
International Search Report for PCT/US 97/09452, dated Oct. 3, 1997.

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