Digital phase-locked loop circuit

Details Digital phase-locked loop circuit Digital phase-locked loop circuit

1995-02-09

1996-01-30

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 370108, 327150, H03D 324

Patent

active

054886414

ABSTRACT:
A digital phase-locked loop circuit includes circuitry for generating substantially periodic recovered clock signals each one corresponding to a discrete amount of delay from a local clock signal. Incremental delay is added or subtracted at each clock generation cycle until the data input signal and the last-generated recovered clock signal are substantially phase-aligned. The circuit includes delay measurement circuitry for dynamically measuring the smallest quantity of delay units required to provide at least a 360 degree phase shift of the local clock signal. The circuitry for generating the recovered clock signals is then constrained to generate clock signals having a maximum delay corresponding to the last-measured quantity of delay.

REFERENCES:
patent: 3931585 (1976-01-01), Barker et al.
patent: 4519071 (1985-05-01), Miller
patent: 4617679 (1986-10-01), Brooks
patent: 4724402 (1988-02-01), Ireland
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5218314 (1993-06-01), Efendovich et al.

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