Process for manufacturing MOS-type integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257 71, 257316, 257377, 257382, 257398, 257399, 257412, 257519, H01L 2976

Patent

active

056963998

ABSTRACT:
A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

REFERENCES:
patent: 3319311 (1967-05-01), Mutter
patent: 3434019 (1969-03-01), Carley
patent: 3461360 (1969-08-01), Barson et al.
patent: 3764396 (1973-10-01), Tarui et al.
patent: 3821776 (1974-06-01), Havamhi et al.
patent: 3845495 (1974-10-01), Cauge et al.
patent: 3849216 (1974-11-01), Herman et al.
patent: 3909320 (1975-09-01), Gauge et al.
patent: 3924265 (1975-12-01), Rodgers
patent: 3950777 (1976-04-01), Tarui et al.
patent: 3986903 (1976-10-01), Watrous, Jr.
patent: 4001860 (1977-01-01), Cauge et al.
patent: 4015278 (1977-03-01), Fukuta
patent: 4055884 (1977-11-01), Chakrapani
patent: 4072975 (1978-02-01), Ishitani
patent: 4145700 (1979-03-01), Jambotkar
patent: 4145703 (1979-03-01), Blanchard et al.
patent: 4148047 (1979-04-01), Hendrickson
patent: 4190850 (1980-02-01), Tihanvi et al.
patent: 4246593 (1981-01-01), Bartlett
patent: 4344081 (1982-08-01), Pao et al.
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4412242 (1983-10-01), Herman et al.
patent: 4549193 (1985-10-01), Malhi et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4604641 (1986-08-01), Konishi
patent: 4663645 (1987-05-01), Komori et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4719184 (1988-01-01), Cantarelli et al.
patent: 4786614 (1988-11-01), Cogan
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 4918501 (1990-04-01), Komori et al.
patent: 4931408 (1990-06-01), Hshieh
patent: 5004701 (1991-04-01), Motokawa
patent: 5098855 (1992-03-01), Komori et al.
patent: 5153143 (1992-10-01), Schlais et al.
patent: 5192707 (1993-03-01), Hodges et al.
patent: 5194924 (1993-03-01), Komori et al.
patent: 5338961 (1994-08-01), Lidow et al.
Integrated Circuits Laboratory, Stanford Electronics Laboratories, Standford University, Standford, CA, Michael Donald Pocha, Mar. 1976, Technical Report No. 4956-1, pp. 229-240 "High Voltage Double Diffused MOS Transistors for Integrated Circuits".
IEEE Journal of Solid-State Circuits, vol. SC11, No. 4, Aug. 1974, Isao Yoshida, et al., pp. 472-477 "A High Power MISFIT with a Vertical Drain Electrode and a Meshed Gate Structure".
IEEE Journal of Solid-State Circuits, vol. SC-11, No. 5, Oct. 1976, Michael D. Pocha, pp. 718-726 "A Computer-Aided Design Model for High-Voltage Double Diffused MOS (DMOS) Transistors".
Exhibit IV, Laid Open Patent Specification No. 85073/80; Laid Open Date Jun. 26, 1980; Patent Application No. 162677/74 (divided from Pat. Appln. No. 9713/74) Patent Application Date Jan. 24, 1975, Isao Yoshida.
Patent Abstract of Japan, vol. 16, No. 185 (E-1197) May 6, 1992.
Patent Abstract of Japan, vol. 9, No. 35 (E-296) ((1758) Feb. 14, 1985.
IEDM 1983 Dec. 5-7, 1983, New York pp. 526-529, J.Y.-T.Chen `AN N-Well CMOS with Self-Aligned Channel Stops`.
IBM TDB, vol. 26, No. 3B, Aug. 1983, pp. 1318-1322, N. Lu `High-Capacitance Dynamic RAM Cell Using Buried Polysilicon Electrodes and Buried Oxide MOS Transistors`.
European Search Reported issued in EP 92 11 8785.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for manufacturing MOS-type integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for manufacturing MOS-type integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing MOS-type integrated circuits will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1610030

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.