Semiconductor memory device responsive to hierarchical internal

Static information storage and retrieval – Powering

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36518909, 365227, 36523003, G11C 700

Patent

active

056047070

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate, a plurality of memory blocks, first and second substrate potential generating circuits and a select circuit. The semiconductor substrate includes a plurality of wells corresponding to the memory blocks. Each memory block includes a plurality of memory cells formed on corresponding wells. The select circuit supplies to the well of the activated memory block a deep substrate potential generated by the first substrate potential generating circuit, and supplies to the well of the unselected memory block a shallow substrate potential generated by the second substrate potential generating circuit. Thereby, the minimum operation in the inactive memory block is ensured in spite of the fact that a power consumption of the inactive memory block is reduced.

REFERENCES:
patent: 4691304 (1987-09-01), Hori et al.
patent: 5278786 (1994-01-01), Kawauchi et al.
patent: 5282171 (1994-01-01), Tokami et al.
"Subthreshold-Current Reduction Circuits for Multi-Gigabit Dram's" by Takeshi Sakata et al., Symposium on VLSI Circuits '93 pp. 45-46.

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