Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1998-06-08

2000-05-02

Phan, Trong

Static information storage and retrieval

Read/write circuit

Having fuse element

365200, G11C 700

Patent

active

060580623

ABSTRACT:
A semiconductor memory circuit comprises a plurality of redundancy address setting circuits and a decode circuit. Each of the redundancy address setting circuits has a first fuse coupled between a first voltage potential node and a first node, a second fuse coupled between the first node and a second node and a transistor coupled between the second node and a second voltage potential node. The decode circuit is coupled to the first nodes of each individual redundancy address setting circuits, for decoding signals which are applied to the first node and outputting a redundancy address signal according to the state of the first and second fuses.

REFERENCES:
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 5387823 (1995-02-01), Ashizawa
patent: 5471426 (1995-11-01), McClure
patent: 5471427 (1995-11-01), Murakami et al.
patent: 5696723 (1997-12-01), Tukahara
patent: 5768196 (1998-06-01), Bloker et al.
patent: 5828624 (1998-10-01), Baker et al.

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