Multi-bit-per-cell and analog/multi-level non-volatile memories

Details Multi-bit-per-cell and analog/multi-level non-volatile memories Multi-bit-per-cell and analog/multi-level non-volatile memories

1998-12-31

2000-05-02

Nelms, David

Static information storage and retrieval

Read/write circuit

Erase

36518503, 36518524, 36518533, G11C 700

Patent

active

060580607

ABSTRACT:
Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb. In another embodiment, ground potential is applied to all the unselected word-lines during programming, which requires a programming load line and charge pump able to handle large currents and supply large voltages, respectively, due to the increased combined leakage current on the bit-line.

REFERENCES:
patent: 5297095 (1994-03-01), Sato et al.
patent: 5615153 (1997-03-01), Yiu et al.
patent: 5717632 (1998-02-01), Richart et al.
patent: 5796657 (1998-08-01), Lee et al.
patent: 5821909 (1998-10-01), Yiu et al.

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