Redundancy system for high speed, wide-word semiconductor memori

Details Redundancy system for high speed, wide-word semiconductor memori Redundancy system for high speed, wide-word semiconductor memori

1982-03-03

1984-07-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 10, G11C 1140

Patent

active

044596855

ABSTRACT:
A redundancy system is described for a high speed, wide-word semiconductor memory having first and second arrays of regular memory cells. The system includes a plurality of spare columns of cells, half of which are located adjacent the first array and half of which are located adjacent the second array. The number of spare columns which are adjacent each array is equal to the number of regular columns which are simultaneously selectable by an address input. Circuitry is included for responding to an incoming address representative of a defective regular cell for selecting half the spare columns in the first array in lieu of the regular addressed columns therein, and for selecting half the spare columns in the second array in lieu of the addressed regular columns therein.

REFERENCES:
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4346459 (1982-08-01), Sud et al.

Affiliated with

Also associated with

Rating

Redundancy system for high speed, wide-word semiconductor memori does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundancy system for high speed, wide-word semiconductor memori, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy system for high speed, wide-word semiconductor memori will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1579861