Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-10-29

1997-10-14

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Flip-flop

257301, 365154, G11C 1100

Patent

active

056778660

ABSTRACT:
In a semiconductor memory device constituted by bulk CMOS 6-Tr memory cells, a structure is realized which can maintain a high soft error immunity even if a power-supply voltage is lowered and a cell size is decreased. In order to realize this structure, a semiconductor memory device using a flip-flop which is constituted by CMOS transistors formed on a surface of a semiconductor substrate, includes a trench isolating region which has an interface between a first conductive well and a second conductive well formed in the semiconductor substrate and is formed from the surface of the semiconductor substrate in a direction of depth to have a predetermined planar shape and a predetermined depth, and a trench capacitor formed in the trench isolating region and separately connected to two memory nodes of a memory cell.

REFERENCES:
patent: 4780751 (1988-10-01), Nishimoto
patent: 4845539 (1989-07-01), Inoue
patent: 4873560 (1989-10-01), Sunami
patent: 5066609 (1991-11-01), Yamamoto
patent: 5278459 (1994-01-01), Matsui
patent: 5315543 (1994-05-01), Matsuo
Kudoh et al., "A New Full CMOS SRAM Cell Structure", NEC Corporation, pp. 67-70, (1984).
Hiramoto et al., "A 27 GHz Double Polysilicon Bipolar Technology On Bonded SOI With Embedded 58 .mu.m.sup.2 CMOS Memory Cells For ECL-CMOS SRAM Applications", IEEE, pp. 39-42, (1992).
"Ultra-High-Speed MOS Device", pp. 314-317, Baifu-kan.

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