Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1992-05-28

1994-03-08

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257304, 257371, 257393, 257503, 257532, H01L 2968

Patent

active

052930556

ABSTRACT:
In a CMOS-DRAM, an n-type silicon substrate has a p-type well formed therein, and a DRAM cell array is formed in the p-type well. In a period immediately after an external power supply is turned on, the p-type well is in a substantially floated condition. A predetermined time after the external power supply is turned on, the p-type well is applied with a predetermined DC voltage generated by a well voltage generating circuit. The CMOS-DRAM has a selective grounding circuit. When the external power supply is turned on, the selective grounding circuit forcibly grounds the plate electrode of the DRAM cell array for a predetermined period of time. Therefore, an increase in the well voltage at the cell array region, which increase may occur due to the capacitive coupling, is prevented when the power supply is turned on. Accordingly, adverse effects arising from the increase in the well voltage are prevented.

REFERENCES:
patent: 4571505 (1986-02-01), Eaton, Jr.
patent: 5079613 (1992-01-01), Sawada et al.

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