Medium voltage LDMOS device and method of fabrication

Details Medium voltage LDMOS device and method of fabrication Medium voltage LDMOS device and method of fabrication

1994-12-12

1998-04-07

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257341, 257401, H01L 2702

Patent

active

057367663

ABSTRACT:
An LDMOS transistor (10) having a medium breakdown voltage and low Rsp includes a high voltage (n-) Nwell (38); a low voltage (n+) Nwell (42) formed in the high voltage Nwell (38); a drain region (64) formed in the low voltage Nwell (42); a Dwell (44) formed in the Nwell (70), the DWELL (46) including a p region (46) forming the backgate and a source region (48), a channel region (46a) defined between an edge of the source region (48) and an edge of the p region (46); and a gate (58) extending over the channel region (46a). Gate (58) extends onto a field oxide region (54) formed using a minimum photolithographic nitride opening to reduce the length of the drift region thus reducing Rsp. Rsp is also reduced by the addition of low voltage Nwell (42) to the drift region since low voltage Nwell (42) is more heavily doped than high voltage Nwell (38) thus reducing Rdson. The low voltage Nwell (42) added to the drift region also provides a reduction in breakdown voltage BV by increasing the field in the curvature region of the Dwell (46). Fabrication of transistor (10) is compatible with VLSI processes.

REFERENCES:
patent: 4922327 (1990-05-01), Mena et al.
patent: 5191401 (1993-03-01), Shirai et al.
patent: 5430316 (1995-07-01), Contiero et al.

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