Static information storage and retrieval – Systems using particular element – Semiconductive
Patent
1993-02-05
1995-04-11
LaRoche, Eugene R.
Static information storage and retrieval
Systems using particular element
Semiconductive
365190, 365154, 365156, 257372, 257373, 257376, 257369, G11C 1140
Patent
active
054065135
ABSTRACT:
A CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. The circuit architecture of the present invention can be utilized with N-Well, P-Well and dual Well processes. For example, the circuit is described relative to an N-Well process. An N-Well is formed in a p-type substrate. A network of p-channel transistors are formed in the N-Well and a network of n-channel transistors are formed in the p-type substrate. A continuous P+guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and the N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between the p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolars forming a parasitic SCR and also act as additional collectors of radiation induced current. Single event upset immunity is improved by forming duplicate functions in an n-channel network and a p-channel network. N-channel control transistors are coupled to control p-channel load transistors and p-channel control transistors are coupled to control n-channel load transistors.
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Cameron Kelly
Canaris John
Whitaker Sterling
Hoang Huan
LaRoche Eugene R.
The University of New Mexico
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