Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1993-06-07
1995-04-11
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
326121, 326 21, 327543, H03K 190175, H03K 190948
Patent
active
054061407
ABSTRACT:
A voltage translator is provided that translates a lower voltage to a higher voltage, for example, a 3.3 V voltage to a 5.0 V voltage. The 3.3 V voltage is received on source/drain terminal N1 of an NMOS transistor. The transistor gate is at 3.3 V. The other source/drain terminal N2 of the transistor is connected to an input of a CMOS inverter powered by 5.0 V. The inverter output is connected to the gate of a PMOS transistor connected between 5.0 V and terminal N2. The PMOS transistor pulls terminal N2 to 5.0 V when terminal N1 is at 3.3 V. The same translator is suitable for translating a 5.0 V voltage on terminal N1 to 3.3 V on terminal N2 if the inverter is powered by 3.3 V and the PMOS transistor is connected between 3.3 V and terminal N2. Also, an output driver is provided in which a voltage protection circuitry prevents charge leakage from the driver output terminal to the driver's power supply when the voltage on the bus connected to the output terminal exceeds the power supply voltage.
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Duncan Richard L.
Wert Joseph D.
Koestner Ken John
National Semiconductor Corporation
Nelson H. Donald
Pitruzzella Vincenzo D.
Santamauro Jon
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