Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-12-05
1997-06-24
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Testing
365195, 365196, 365221, G11C 700, G11C 2900
Patent
active
056423187
ABSTRACT:
The present invention provides a system for testing a memory array and corresponding support circuitry. The present invention provides a highly efficient testing mode to be entered that allows any type of advanced testing to be performed on the memory array without regard to the restrictions imposed by the various status flags that may be present. The testing mode can be entered by a completely user-defined mechanism. During this testing mode, the user has complete control over the contents of the memory array and can also have complete control over the positioning of the write word line with respect to the read word line without, for example, any write-read word line pointer equality signals being generated. In one example of the present invention used in a FIFO, testing times required for data retention testing are reduced from approximately six seconds to approximately 500.mu. seconds for each part tested, since the entire internal memory core of the FIFO can be tested in a single pass without regard to the external depth of the FIFO.
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Hawkins Andrew L.
Knaack Roland T.
Rodell, Jr. Richard A.
Cypress Semicondcutor Corporation
Yoo Do Hyun
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