Method and apparatus of redundancy for non-volatile memory integ

Details Method and apparatus of redundancy for non-volatile memory integ Method and apparatus of redundancy for non-volatile memory integ

1996-05-21

1997-06-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, 3652257, 36523006, 36518509, G11C 700, G11C 800, G11C 1134

Patent

active

056423160

ABSTRACT:
A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.

REFERENCES:
patent: 4538245 (1985-08-01), Smarandoiu et al.
patent: 4546454 (1985-10-01), Gupta et al.
patent: 4617651 (1986-10-01), Ip et al.

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