Virtual memory system with hardware TLB and unmapped software TL

Details Virtual memory system with hardware TLB and unmapped software TL Virtual memory system with hardware TLB and unmapped software TL

1996-04-29

1998-11-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

G06F 1210

Patent

active

058359648

ABSTRACT:
A virtual memory system includes a hardware-implemented translation lookaside buffer (HTLB) as well as a software-implemented translation lookaside buffer (VTLB). The VTLB is in the system's unmapped memory. The system further includes a plurality of address maps, corresponding to an operating system kernel and to individual tasks executing within the system. The kernel has an address space which includes both mapped and unmapped memory. The address maps corresponding to the individual tasks are stored in the mapped memory of the kernel's address space. The address map corresponding to the kernel itself, however, is stored in the kernel's unmapped memory. HTLB misses are handled by referring to the VTLB. VTLB misses are handled by referring to an appropriate one of the address maps. The code for handling these misses resides in unmapped memory of the kernel's address space. This arrangement prevents recursive TLB misses, without requiring permanent or "wired" VTLB entries. Because there are no permanent VTLB entries, the VTLB can have a simple and efficient structure, and its size can be bounded. As a further feature, the address maps are associated with both spin locks and mutex locks. A routine which modifies an individual address map first acquires the mutex lock associated with the address map and performs initial examination of the address map. Once the routine is ready to make actual modification, it also acquires the spin lock. By having the two types of locks, the majority of the routine can be preemptible. Only the portion of the routine which actually modifies the address map needs to be non-preemptible.

REFERENCES:
Kavita Bala, M. Frans Kaashoek, and William E. Weihl, "Software Prefetching and Caching for Translation Lookaside Buffers", Proceedings of the First Usenix Symposium on Operating Systems Design and Implementation (Nov., 1994), pp. 243-253.
Rashid et al., Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures, Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 5-8, 1987, pp. 31-39.

Affiliated with

Also associated with

Rating

Virtual memory system with hardware TLB and unmapped software TL does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual memory system with hardware TLB and unmapped software TL, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual memory system with hardware TLB and unmapped software TL will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1529420