Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-04-25
1999-01-12
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711124, 711144, 711147, 711167, 39520043, G06F 1200, G06F 1300
Patent
active
058601082
ABSTRACT:
In a clustered multi-processor system and method, first and second clusters are connected between first and second directories. The first directory checks whether an address of a request on a first system bus coincides with an address of a request from the second directory. When the first directory detects the coincidence, the first directory cancels the request on the first system bus, and reissues the request. Since the first system bus and a second system bus have a different clock phase, the requests are checked without overlapping.
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C.K. Tang; "Cache System Design in the Tightly Coupled Multiprocessor System"; National Computer Conference, 1976, pp. 749-753.
D. Lenoski et al.; "Design of Scalable Shared-Memory Multiprocessors: The DASH Approach"; I.E.E.E. (1990) Computer Systems Laboratory, Stanford University, CA pp. 62-67.
NEC Corporation
Swann Tod R.
Thai Tuan V.
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