Multi-level memory circuits and corresponding reading and writin

Details Multi-level memory circuits and corresponding reading and writin Multi-level memory circuits and corresponding reading and writin

1997-01-30

1999-01-12

Yoo, Do Hyun

Static information storage and retrieval

Systems using particular element

Ternary

36518902, G11C 700

Patent

active

058597956

ABSTRACT:
The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.

REFERENCES:
patent: 5218569 (1993-06-01), Banks
patent: 5671388 (1997-09-01), Hasbun
Takahiro Hanyu et al., Systems and Computers in Japan, vol. 21, Nov. 12, 1989, "Design of a Multiple-Valued Associative Memory", pp. 23-32.

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