Integrated semiconductor dynamic memory

Details Integrated semiconductor dynamic memory Integrated semiconductor dynamic memory

1977-09-22

1979-01-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Differential sensing

365 72, 365189, 365149, G11C 706

Patent

active

041330480

ABSTRACT:
A memory using MOS (metal-oxide-semiconductor) structures comprises a memory matrix of an even number of memory cells divided into two groups. One terminal of every cell is connected to a respective select bus located along a memory matrix line. The other terminal of memory cells in a first group of memory cells is connected to a first number bus of the respective matrix column and the other terminal of memory cells in a second group of memory cells is connected to a second number bus of the respective matrix column located parallel to the first number bus. Memory cells of different groups are connected to respective number buses so that along the column they are interspaced by at least one memory cell. Data terminals of column differential amplifiers are connected to the respective number buses of the respective matrix columns. At least one of the number buses of every column is connected, via a respective matrix column select key, to numeric data input/output buses.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4031522 (1977-06-01), Reed et al.

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