Synchronous DRAM cache using write signal to determine single or

Details Synchronous DRAM cache using write signal to determine single or Synchronous DRAM cache using write signal to determine single or

1999-02-10

1999-09-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

3652385, G06F 1300

Patent

active

059537396

ABSTRACT:
A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and input/output connections are distributed around the memory to increase speed. Page access operations are controlled to allow either single or burst writes.

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