Electronic digital logic circuitry – Interface – Current driving
Patent
1997-04-14
1999-01-12
Santamauro, Jon
Electronic digital logic circuitry
Interface
Current driving
326 82, H03K 19082
Patent
active
058595457
DESCRIPTION:
BRIEF SUMMARY
This invention relates to bus line buffering and in particular to buffering for a two-way bus.
Devices connected to an open-collector bus (or an open-drain bus) must normally be able to read the status (high/low) of the bus lines, as well as be able to force them low by means of open-collector (or open-drain) drivers. It is often desirable to have buffer circuitry between the device, which may be an integrated circuit or a local sub-bus system, for example, and the bus, for one or more reasons, such as the following reasons: This would typically be the case if the device contains CMOS circuitry and the bus lines extend outside of a shielding cabinet. low. it is in the power-off state, or while it is entering or leaving the power-off state.
Such buffering is easy to implement if the device D has separate terminals for input and output, ie one terminal 2 for reading an open-collector bus line (external line 4) and a different terminal 3 for forcing the line low, as illustrated in FIG. 1. There is an input buffer 5 connected between external line 4 and terminal 2 and an output buffer 6 connected between terminal 3 and line 4. The symbol in buffer 6 denotes an open-collector output.
However, if the input and output are handled by the same terminal, which is often the case, then buffering is more complicated. Simply paralleling an input buffer 5 with an output buffer 6 as shown in FIG. 2 would cause the line 4 to be locked low. Both buffers will remain low indefinitely as each one supplies a low input to the other one.
To overcome the problem, the output buffer 6 must be able to distinguish between two different causes for a low level on the device side, ie on the internal line:
In Case A the output buffer 6 must pull the external line 4 low, but in Case B it must not.
There are commercially available buffer circuits which make this distinction by way of current sensing and current amplification. If a positive current is flowing into the device D on the internal line 7 (Case A), then the output buffer will sink a multiple of that current on the external line. The disadvantages of these buffer circuits are cost and the fact that the current amplification also causes capacitance amplification. The external line "sees" the internal capacitance multiplied by the current amplification factor. Furthermore, these buffer circuits may not be consistent with reasons 1 and/or 3 referred to above.
The present invention aims to provide a solution which does not suffer from the aforementioned disadvantages.
According to one aspect of the present invention there is provided a buffer circuit for use between a bus line and an input/output terminal of a device capable of reading the status of the bus line and driving it low, the buffer circuit including a line which is connected in use to the terminal, an input buffer in parallel with an output buffer, the input of the input buffer being connected to the output of the output buffer and connected in use to the bus line, the output of the input buffer being connected to the input of the output buffer and to the line, and the buffer circuit being such that two logical levels of the same type which may be present on the line and have different sources are distinguishable from one another, characterised in that the output buffer is in the form of a comparator which compares any said logical level with a reference level and interprets it as arising from a first source if it is less that the reference level or as arising from a second source if it is greater than the reference level, and the output buffer is such as to distinguish between two logical low levels on the line, whose sources are the device or the input buffer, respectively, pulling the line low, and wherein the output buffer is such as to pull the bus line low only when the device is pulling the line low.
According to another aspect of the present invention there is provided a method of buffering a connection between a bus line and a device capable of reading the status of the bus line and driving it low, including the ste
REFERENCES:
patent: 5214330 (1993-05-01), Okazaki
patent: 5248908 (1993-09-01), Kimura
patent: 5587824 (1996-12-01), Asprey
patent: 5736870 (1998-04-01), Greason et al.
ICL Systems AB
Le Don Phu
Santamauro Jon
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