High speed clock recovery circuit using complimentary dividers

Details High speed clock recovery circuit using complimentary dividers High speed clock recovery circuit using complimentary dividers

1996-06-20

1999-09-14

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327156, 327157, 331 25, H03D 324, H03L 706

Patent

active

059533862

ABSTRACT:
A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.

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