Method and apparatus for remapping addresses for redundancy

Details Method and apparatus for remapping addresses for redundancy Method and apparatus for remapping addresses for redundancy

1998-09-03

1999-09-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, G11C 700

Patent

active

059532696

ABSTRACT:
A semiconductor memory device includes a memory array having first and second columns, each column having a plurality of memory locations associated therewith and being identified by first and second column addresses, respectively. Column address decoding circuitry receives column address signals and selects at least one column memory array. The column address decoding circuitry is programmable such that the first column is identified by the second column address and the second column may be identified by the first column address.

REFERENCES:
patent: 5243570 (1993-09-01), Saruwatari
patent: 5325334 (1994-06-01), Roh et al.
patent: 5696723 (1997-12-01), Tukahara
patent: 5706231 (1998-01-01), Kokubo
patent: 5708612 (1998-01-01), Abe

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