Method of forming an improved planar isolation structure in an i

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation

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438444, 438446, 438447, H01L 2176

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058343601

ABSTRACT:
A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.

REFERENCES:
patent: 4026740 (1977-05-01), Owen, III
patent: 4160987 (1979-07-01), Dennard et al.
patent: 4266985 (1981-05-01), Ito et al.
patent: 4407696 (1983-10-01), Han et al.
patent: 4508757 (1985-04-01), Fabricius et al.
patent: 4551910 (1985-11-01), Patterson
patent: 4553314 (1985-11-01), Chan et al.
patent: 4561172 (1985-12-01), Slawinski et al.
patent: 4563227 (1986-01-01), Sakai et al.
patent: 4637128 (1987-01-01), Mizutani
patent: 4755477 (1988-07-01), Chao
patent: 4842675 (1989-06-01), Chapman et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5130268 (1992-07-01), Liou et al.
patent: 5151381 (1992-09-01), Liu et al.
patent: 5192707 (1993-03-01), Hodges et al.
patent: 5210056 (1993-05-01), Pong et al.
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5264724 (1993-11-01), Brown et al.
patent: 5286672 (1994-02-01), Hodges et al.
patent: 5296411 (1994-03-01), Gardner et al.
patent: 5310692 (1994-05-01), Chan et al.
patent: 5318922 (1994-06-01), Lim et al.
patent: 5393692 (1995-02-01), Wu
patent: 5410176 (1995-04-01), Liou et al.
patent: 5440166 (1995-08-01), Dixit et al.
patent: 5457067 (1995-10-01), Han
patent: 5470783 (1995-11-01), Chiu et al.
patent: 5472906 (1995-12-01), Shimizu et al.
patent: 5512509 (1996-04-01), Han
patent: 5538916 (1996-07-01), Kuroi et al.
patent: 5612248 (1997-03-01), Jeng
S. Marshall, et al., "Dry Pressure Local Oxidation of Silicon for IC Isolation", Journal of the Electrochemical Society, v. 122, No. 10, Oct. 1975.
R. Zeto, et al., "Low Temperature Thermal Oxidation of Silicon by Dry Oxygen Pressure above 1Atm", The Electrochemical Society, V. 122, No. 10, Oct. 1975.
Lin, et al., "Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", J. Electrochem. Soc., v. 138, No. 7, Jul. 1991, pp. 2145-2149.
Irene, et al., "Residual Stress, Chemical Etch Rate, Refractive Index, and Density Measurements on SiO, Films Prepared Using High Pressure Oxygen", pp. 396-399, J. Electrochem. Soc., Feb. 1980.
VIB-1, "Integration of Poly Buffered Locos and Gate Processing for Submicrometer Isolation Technique", Juengling et al., IEEE Transactions on Electron Devices, V. 38, No. 12, Dec. 1991, p. 2721.
Kangar, et al., "An Integrated Isolation/Gate Process for Sub-Quarter Micron Technologies", pp. 141-142, May 1993 Symposium on VLSI Technology.
Josquin, et al., "The Oxidate Inhibition in Nitrogen-. . . Silicon", pp. 1803-1810, V. 129, No. 8, Aug. 1982, J. Electrochem. Soc.
Sung, et al., "Reverse L-Shape Sealed Poly-Buffer LOCOS Technology", IEEE Electron Device Letters, vol. 11, No. 11, Nov., 1990, pp. 549-551.
Eklund, et al., "A 0.5-.mu. BICOMS Technology for Logic and 4Mbid-class SRAM's", pp. 425-428, 1989 IEEE.

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