System and method for error correction code generation

Details System and method for error correction code generation System and method for error correction code generation

1994-11-28

1996-07-02

Beausoliel, Jr., Robert W.

39518505, G01R 3128, G06F 1100

Patent

active

055331890

ABSTRACT:
Error correction code ("CECC") generation within a directory or memory controller is distributed between generation of an ECC for the tag and status portions of a directory entry and then summed to produce the ECC bits for the directory entry. The ECC generation may be performed for entries with respect to a cache for a uniprocessor or multiprocessor system or for system memory within such a data processing system. The ECC generation of the present invention reduces by one or more cycles the required time utilized for updating a directory entry.

REFERENCES:
patent: 4167727 (1979-09-01), Anderson
patent: 4168486 (1979-09-01), Legory
patent: 4942578 (1990-07-01), Nakamura
patent: 5146461 (1992-09-01), Duschatko et al.
patent: 5146588 (1992-09-01), Crater et al.
patent: 5164944 (1992-11-01), Benton
patent: 5325508 (1994-06-01), Parks et al.
patent: 5361267 (1994-11-01), Godiwala
Ooi et al., Fault Tolerant Architecture in a Cache Memory Control LSI, IEEE Journal of Solid-State Circuits, vol. 27 No. 4 Apr. 1992, pp. 507-514.

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