Digital phase alignment and integrated multichannel transceiver

Details Digital phase alignment and integrated multichannel transceiver Digital phase alignment and integrated multichannel transceiver

1993-11-12

1996-07-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 327141, H03D 324

Patent

active

055330720

ABSTRACT:
A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

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