Short circuit current free dynamic logic clock timing

Details Short circuit current free dynamic logic clock timing Short circuit current free dynamic logic clock timing

1995-04-17

1997-06-24

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, H03K 19096

Patent

active

056420617

ABSTRACT:
An apparatus and method for providing short circuit current free dynamic logic building blocks comprising P-logic and N-logic dynamic domino building blocks having separate clocks for driving the P-logic and N-logic evaluate and pre-charge stages. The P-logic building gates are pre-charged to a zero volt output and upon the transition from high to low on the input line, will provide a high output during the evaluation cycle. Conversely, the N-logic building blocks are pre-charged with a high output level and upon the transition of a low to high input to the building block device, will provide a low output signal during the evaluation period. Both building block types are pre-charged again at the end of the evaluation period to provide an inherently glitch-free dynamic logic device. Separate evaluate and charge clock signals are provided to each of the P-logic and N-logic building blocks which are configured to provide a non-overlapping charge and evaluation cycle. The active portions of the pre-charge, evaluate cycles, and the transitions between are made mutually exclusive. A static latch is provided for use in DC operations upon shut off of the charge clock. In an alternative embodiment, a dynamic latch is provided for use in a minimal frequency clocking embodiment of the dynamic building blocks where charge cycles are sufficiently frequent to compensate for charge decay.

REFERENCES:
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patent: 4827160 (1989-05-01), Okano
patent: 5144163 (1992-09-01), Matsuzawa
patent: 5329176 (1994-07-01), Miller, Jr.
patent: 5378942 (1995-01-01), Wu
patent: 5453708 (1995-09-01), Gupta

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