Clock generator

Details Clock generator Clock generator

1996-02-21

1997-06-24

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

327291, H03K 19096

Patent

active

056420609

ABSTRACT:
A clock generator comprising inverters I.sub.1A, I.sub.1B, I.sub.2A, a NOR circuit NO.sub.1, an inverter I.sub.3A and a NOR circuit NO.sub.2 . . . which transmit sequentially an input clock signal A, D flip-flops DF.sub.1, DF.sub.2, DF.sub.3 . . . which latches the input clock signal at different positions during transmission, NAND circuits N.sub.1, N.sub.2, N.sub.3 . . . which output intermediate signals A1, A2, A3 . . . in response to latch data of the D flip-flops DF.sub.1 DF.sub.2, DF.sub.3 . . . and the input clock signal, and a multi-input AND circuit AN.sub.0 to which the intermediate signals A1, A2, A3 are inputted, and being configured so as to input each signal based on the latch data of adjacent D flip-flops to the NOR circuits NO.sub.1 and NO.sub.2, thereby duty of an output clock signal generated based on the input clock signal does not become small even when the input clock signal having high frequency is inputted.

REFERENCES:
patent: 5289050 (1994-02-01), Ogasawara
patent: 5389830 (1995-02-01), Buckingham
patent: 5420467 (1995-05-01), Huott
patent: 5475322 (1995-12-01), MacDonald

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