Semiconductor memory device which can be programmed to indicate

Details Semiconductor memory device which can be programmed to indicate Semiconductor memory device which can be programmed to indicate

1994-09-21

1996-01-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365203, G11C 1300

Patent

active

054870410

ABSTRACT:
A cache memory device includes a plurality of memory cell arrays each including a plurality of memory cell rows, a plurality of first fuse elements each provided corresponding to each memory cell row and disconnected when the corresponding memory cell row is defective, and a plurality of second fuse elements each provided corresponding to each memory cell array and disconnected when the corresponding memory cell array is defective. As a result, the cache memory device can indicate that, when a bit line of a certain memory cell array is defective, the memory cell array is defective by disconnecting a second fuse element corresponding to the memory cell array.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 5199033 (1993-03-01), McGeoch et al.
"Computer Architecture A Quantitative Approach", Hennessy et al., Morgan Kaufamnn Publishers Inc, pp. 414-415.
"Nonvolatile and Application-Specific Memories", Cho et al., ISSCC Digest of Technical papers, pp. 50-51.

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