Stress mode circuit for an integrated circuit with on-chip volta

Details Stress mode circuit for an integrated circuit with on-chip volta Stress mode circuit for an integrated circuit with on-chip volta

1992-11-30

1996-07-02

Callahan, Timothy P.

Electronic digital logic circuitry

Interface

Logic level shifting

327530, 327 65, 327 72, 327 70, 365201, H03K 1700

Patent

active

055326188

ABSTRACT:
A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

REFERENCES:
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patent: 5349559 (1994-09-01), Park et al.
patent: 5367491 (1994-11-01), Han et al.
patent: 5436582 (1995-07-01), Ikeda
Horiguchi et al., "Dual-Operating Voltage Scheme for a Single 5V 16 Mbit DRAM" IEEE J. Solid State Cir., vol. 23. pp. 1128-1132 (Oct. 1988).
Hori et al., "An Experimental 1 Mbit DRAM Based on High S/N Design," IEEE J. Solid State Cir., vol. SC-19 (Oct. 1984).
Gray & Meyer, Analysis of Analog Integrated Circuits, 20 ed. 1977, 1984, pp. 65-67, 705-709, 726-727.
Mao et al., A New On-chip Voltage Regulator for High Density CMOS DRAMs, 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 108-109.

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