Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-04-04
1999-09-14
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365200, G11C 2900, C11C 700
Patent
active
059517026
ABSTRACT:
A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell. Reading causes a small voltage difference to be generated on the scan-data bit lines which is sensed by a sense amplifier. Only two n-channel transistors are added to a macrocell to make the macrocell testable. Thus testing is added with minimal area, cost, and delay to the macrocell.
REFERENCES:
patent: 5303197 (1994-04-01), Miyashita et al.
patent: 5305264 (1994-04-01), Takahashi
patent: 5406216 (1995-04-01), Millman et al.
patent: 5414714 (1995-05-01), Gladden et al.
patent: 5450418 (1995-09-01), Ganapathy
patent: 5463338 (1995-10-01), Yurash
patent: 5517451 (1996-05-01), Okuzawa
patent: 5559745 (1996-09-01), Banik
Blomgren James S.
Cohen Earl T.
Lim Hank
Pan Jengwei
Vigil Peter J.
S3 Incorporated
Tu Trinh L.
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