Signal processor

Boots – shoes – and leggings

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Details

364574, 371 62, G06F 946

Patent

active

057272166

ABSTRACT:
A signal processor having excellent noise resistance characteristics while maintaining superior synchronizing characteristics for hardware interrupt processes. Signal A output from a port REM of a high order CPU is input in parallel as signals B and C to an interrupt port INT of a motor drive control CPU, and to a normal input port Pi, respectively. Timers x and y are started at the same time as interrupt signal B falls, timer y counts up to time Y before time X set by timer x, and at that time a determination is made as to whether or not signal C input to port Pi and signal B input to port INT are identical. If signals B and C are identical, they are normal input signals, and pulse signals are output from ports P0-P3 after time X elapses. If signals B and C are different, a pulse signal is not output from the ports P0-P3.

REFERENCES:
patent: 4550382 (1985-10-01), Federico et al.
patent: 4631683 (1986-12-01), Thomas et al.
patent: 5018342 (1991-05-01), McClure et al.

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