Semiconductor memory device capable of preventing data of non-se

Details Semiconductor memory device capable of preventing data of non-se Semiconductor memory device capable of preventing data of non-se

1989-12-04

1991-06-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365185, 365227, G11C 1140, G11C 1300

Patent

active

050254170

ABSTRACT:
A semiconductor memory device includes a first power source terminal supplied with a first power source voltage for data readout, a second power source terminal supplied with a second power source voltage for data write-in, memory cells formed of a floating gate type MOS transistor, a voltage switching circuit for selectively outputting one of the first and second power source voltages supplied to the first and second power source terminals, a voltage lowering circuit for lowering the second power source voltage supplied to the second power source terminal and outputting the lowered voltage, a gate potential control circuit connected to receive an output voltage of the voltage switching circuit as a power source voltage and supplies an output to the gate of the memory cell, and a drain potential control circuit connected to receive an output voltage of the voltage lowering circuit as a power source voltage and supplies an output to the drain of the memory cell. The second power source voltage for data write-in supplied to the second power source terminal is lowered by the power source voltage lowering circuit and is then supplied to the drain of the memory cell via the drain potential control circuit.

REFERENCES:
Kayama et al., "A 100ns 4Mbit (512K.times.8 bit) CMOS EPROM," Digest of ESSCIRC '88, pp. 23-25 (Sep. 1988).

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