DRAM system with simultaneous burst read and write

Details DRAM system with simultaneous burst read and write DRAM system with simultaneous burst read and write

1997-09-19

2000-07-04

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711169, 36518904, 36518905, G06F 1200

Patent

active

06085300&

ABSTRACT:
A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for reading but also for writing.

REFERENCES:
Sunaga et al.; A Full Bit Prefetch Architecture for Synchronous DRAM's; IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1995, pp. 998-1005.
Sunaga; A Full Bit Prefetch DRAM Sensing Circuit; IEEE Journal of Solid-State circuits, vol. 31, No. 6, Jun. 1996, pp. 767-772.

Affiliated with

Also associated with

Rating

DRAM system with simultaneous burst read and write does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM system with simultaneous burst read and write, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM system with simultaneous burst read and write will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1496318