Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1999-11-08
2000-07-04
Tran, Andrew Q.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523003, 365205, 36523006, 365233, G11C 700
Patent
active
060848073
ABSTRACT:
A memory device with global redundancy repair architecture and method of employing same. In the memory device containing blocks of normal memory cells, redundant cells are assembled in one block called a special block. One or more sense amplifiers are coupled to each block, including the special block. The sense amplifiers connected to the special block are not shared between the special block and a neighboring normal block or any other normal block. Addresses of defective cells are stored in fuse boxes that assign the defective address to a repair cell within the special block. The fuse boxes can assign any normal cell in the array to a repair cell in the special block. In the method, a selected memory block is operated whether the selected word line needs repair or not without waiting for a comparison signal from the fuse box. The special block is always operated as if it is selected. If a block adjacent the special block is selected, there is no problem since the special block does not share a sense amp with adjacent blocks. Since the block containing the repair cells is always turned on, toggling of the sense amps and consequent current is greatly reduced.
REFERENCES:
patent: 4718041 (1988-01-01), Baglee et al.
patent: 4763305 (1988-08-01), Kuo
patent: 5687108 (1997-11-01), Proebsting
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