Synchronous memory with programmable read latency

Details Synchronous memory with programmable read latency Synchronous memory with programmable read latency

1999-01-06

2000-07-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 700

Patent

active

060848057

ABSTRACT:
The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit includes a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also includes a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also presented.

REFERENCES:
patent: 4445204 (1984-04-01), Nishiguchi
patent: 5311483 (1994-05-01), Takasugi
patent: 5729502 (1998-03-01), Furutani et al.

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