Double coding mask read only memory (mask ROM) for minimizing ba

Details Double coding mask read only memory (mask ROM) for minimizing ba Double coding mask read only memory (mask ROM) for minimizing ba

1998-05-04

2000-07-04

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, 257408, 257324, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

06084275&

ABSTRACT:
The present invention includes a normal NMOS device region and a NMOS cell region for coding. An isolation structure is formed between the normal NMOS device region and the NMOS cell region. A gate oxide is formed on the normal NMOS device region and a coding oxide is formed on the NMOS cell region. A polysilicon layer is formed on the gate oxide. Gates are respectively formed on the polysilicon layer and the coding oxide. Spacers are formed on the side walls of the gates. LDD structures are formed under the spacers and adjacent to the gates. Source and drain regions are formed next to the LDD structures. A p type conductive region is formed adjacent to the surface of the NMOS cell region and under the coding oxide.

REFERENCES:
patent: 5081052 (1992-01-01), Kobayashi et al.
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patent: 5372961 (1994-12-01), Noda
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patent: 5536962 (1996-07-01), Pfiester
patent: 5538906 (1996-07-01), Aoki
patent: 5571739 (1996-11-01), Hong
patent: 5597753 (1997-01-01), Sheu et al.
patent: 5793086 (1998-08-01), Ghio et al.

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