Fabrication process for copper structures

Details Fabrication process for copper structures Fabrication process for copper structures

1999-08-12

2000-07-04

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438637, 438638, 438634, 438700, 257750, 257774, 257762, H01L 214763

Patent

active

060838221

ABSTRACT:
A process for creating a dual damascene opening, in a composite insulator layer, to be used to accommodate a dual damascene copper structure, has been developed. The process features the use of a composite insulator layer, comprised with silicon oxide layers, and with multiple silicon nitride layers, used as stop layers, during selective, anisotropic RIE procedures, used to create the dual damascene opening, in the composite insulator layer. The multiple silicon nitride stop layers, are maintained at minimum thicknesses, to still allow selective formation of the dual damascene opening, however avoiding the capacitance increases, encountered with thicker silicon nitride counterparts. A dual damascene copper structure, formed in the dual damascene opening, exhibits minimum RC delays, as a result of the use of low resistivity copper, and as a result of the use of a minimum of silicon nitride etch stop layers, in the composite insulator.

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patent: 5966634 (1999-10-01), Inohara et al.
patent: 5989997 (1999-11-01), Lin et al.

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