Conditional data pre-fetching in a device controller

Details Conditional data pre-fetching in a device controller Conditional data pre-fetching in a device controller

1996-08-30

1998-06-02

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711213, 395383, G06F 1208

Patent

active

057617180

ABSTRACT:
An algorithm for conditionally pre-fetching data for DRAM access is disclosed. A similar pattern of performing successive block reads of DRAM data in the execution of several types of instructions in a computer system is determined by analyzing CPU signals. These instructions repeatedly read blocks of data from a local memory area. Additional writes to memory or an input/output port may intervene between the repeated block reads. By using the pattern as a condition for pre-fetching data from DRAM into a high speed memory buffer of a memory controller, consecutive memory reads can be completed with zero wait state. The penalty incurred by unconditional pre-fetching of DRAM data is minimized. The conditional pre-fetching mechanism is applicable to other computer peripheral devices.

REFERENCES:
patent: 5586294 (1996-12-01), Goodwin et al.

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