Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-06-07
1998-06-02
Dung, Dinh C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711113, 711210, C06F 1310
Patent
active
057615314
ABSTRACT:
When an input/output request of a channel adapter causes a mishit on a cache and a staging amount by a device adapter reaches a predetermined amount, the cache is set into a hit status and the channel adapter is reactivated. By receiving a hit response, the reactivated channel adapter executes an input and an output for the cache and the staging of the channel adapter in parallel. A defective/alternating track management table which corresponds to track data stored in a cache memory and has each of addresses of a defective track and an alternating track and flag information showing a link state between both of the defective track and the alternating track is provided for an input/output controller. For a retrieving request in which the defective track address is designated, the defective/alternating track management table is retrieved and the corresponding alternating track address is obtained, thereby judging the presence or absence of a registration of a hash table.
REFERENCES:
patent: 4258418 (1981-03-01), Heath
patent: 5329622 (1994-07-01), Belsan et al.
patent: 5586291 (1996-12-01), Lasker et al.
Fueda Wasako
Ohmura Hideaki
Takatsu Kazuma
Dung Dinh C.
Fujitsu Limited
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