Low voltage generator for bitlines

Details Low voltage generator for bitlines Low voltage generator for bitlines

1998-05-26

1999-11-09

Phan, Trong

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518909, 36518911, G11C 1604, G11C 700

Patent

active

059826762

ABSTRACT:
Disclosed is an electrical technique for clamping the bitline voltage above zero volts in a DRAM circuit. The technique may be used in embedded DRAM arrays implemented in logic-based technology employing low threshold voltages. The invention employs a low voltage generator to provide a bitline voltage slightly above zero volts. Applying this slightly elevated level to the input of a DRAM cell access transistor effectively increases the threshold voltage of that transistor and thus limits sub-threshold leakage current. The low voltage generator may be implemented as a cascode circuit with supplemental current sources.

REFERENCES:
patent: 4788663 (1988-11-01), Tanaka et al.
patent: 5117131 (1992-05-01), Ochi et al.
patent: 5132936 (1992-07-01), Keswick et al.
patent: 5200921 (1993-04-01), Okajima
patent: 5206942 (1993-04-01), Ibi
patent: 5253205 (1993-10-01), Eaton, Jr.
patent: 5444659 (1995-08-01), Yokokura
patent: 5777939 (1998-07-01), Won

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