Wire bond packages for semiconductor chips and related methods a

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257666, 257667, 257668, 257691, 257692, 257693, 257697, 257773, 257778, 257787, H01L 2306, H01L 23495, H01L 2302

Patent

active

060139463

ABSTRACT:
A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace. Furthermore, the input/output pads can be on an interior portion of the surface of the semiconductor chip, and the insulating layer can have an opening therein for exposing the input/output pads. Accordingly, a dam on the second surface of the insulating layer can be provided around the opening wherein each of the conductive traces extends from adjacent the opening under the dam to a portion of the insulating layer outside the dam. Related methods and assemblies are also discussed.

REFERENCES:
patent: 4218701 (1980-08-01), Shirasaki
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5661086 (1997-08-01), Nakashima et al.
patent: 5677566 (1997-10-01), King et al.
Crowley et al., Chip-Size Packaging Developments, Chapter 2.15 Tessera, Inc., 1995 TechSearch International Inc., pp. 101-109.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Wire bond packages for semiconductor chips and related methods a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wire bond packages for semiconductor chips and related methods a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wire bond packages for semiconductor chips and related methods a will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1464468

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.