Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-11-17
1998-12-15
Decady, Albert
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711100, G11C 700
Patent
active
058505067
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to memory cards, and more particularly to cards containing a non-volatile memory whose contents are managed (for the writing, erasure and updating of recordings) by a microprocessor.
One of the aims proposed by the present invention is to ensure the greater integrity and greater coherence of the data elements recorded in the non-volatile memory of the card.
When novel applications are developed in the form of programs memorized in the card and performed (i.e., executed) by the microprocessor, it is important to ensure that the data elements preserved in the card are coherent and have an unquestionable meaning with respect to their application. The simplest example here is that of cards used as means of payment: if a data element recorded in the card corresponds to a debit or credit amount, it is imperative that there should be no error in this data element.
The data elements recorded in the non-volatile memory of the card are arranged in files according to known methods. The file has recordings and the recordings are placed at specified physical positions of the memory. A file allocation table determines the locations of the memory occupied. The recordings may be chains, namely each recording will have two parts: a data element and an address of the next recording of the file. Within one and the same file, the data elements are, in principle, coherent with one another and in any case it is possible to check the coherence by examining the contents of the file.
But, sometimes, it is also necessary to ensure the coherence of data elements recorded in several different files. This coherence is not easy to ensure in every case of defective operation.
One of the risks in defective operation, for example, is that of the card being wrenched out of the reader during a write operation. There is a risk that the data might be lost. Such problems, related to errors likely to arise during the transmission of information, have been described in the documents FR-A-2 612 316 and EP-A-0 319 799. It has already been attempted to provide for safety procedures (the locking of critical sequences) to avert this risk. The writing is done in two stages and the writing is validated only if it has taken place properly. But if the wrenching takes place during the write operation, then the fact that there has been an abnormal interruption is preserved in the non-volatile memory and the lost data element is reconstituted when the card is powered again.
However, this writing procedure, although more sophisticated than a simple procedure (and hence lengthier), cannot ensure the coherence of the data elements written in two different files. A simple example may be given: a debit file and a credit file are present and are linked by the fact that any increase on one side must correspond to an equal decrease on the other side.
It will be understood that there is a risk that an untimely power cut might destroy the coherence of the data elements recorded in the two files: for example, there may have been time to record the debit accurately on one side and not the credit on the other side.
Furthermore, to ensure the coherence of data elements that are not written in one and the same operation, it may be necessary to link several operations in one way or another.
OBJECTS AND SUMMARY OF THE INVENTION
It is an aim of the invention to improve the operating safety of chip cards from the viewpoint of the integrity and coherence of the data elements written in the non-volatile memory of these cards.
Accordingly, the present invention provides a method of performing memory operations in a non-volatile memory of a non-volatile memory card comprising the steps of executing a grouping instruction, performing the N successive memory operations, and determining whether the N successive memory operations are to be validated.
The grouping instruction groups together N successive memory operations for comprehensive validation, N being a finite number greater than one. For this purpose, the grouping instruct
REFERENCES:
patent: 4459658 (1984-07-01), Gabbe et al.
patent: 5371886 (1994-12-01), Britton et al.
De'cady Albert
Gemplus Card International
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